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IDT 2016 Tutorials include:
New approaches towards early dependability evaluation of digital integrated systems Abstract Integrated embedded systems are increasingly used in many applications, including critical ones. The fast growing Internet-of-Things markets still increase concerns about reliability, safety and security. Circuits made in up-to-date technologies are more sensitive to perturbations, in spite of manufacturing progress, due to the number of functions implemented in a single chip. Malicious attacks are based on creating errors to take the control of a system and/or steal private data. In this context, an increasing number of designers need to take care, early in the design flow, of consequences of soft errors (i.e., errors in the processed data, without physical defect induced in the chip). The usual means for early evaluating dependability is fault injections. Many approaches and tools have been developed. This tutorial will discuss alternative approaches that lead to optimized evaluation durations (and therefore easier iterations) while providing good accuracy. Presented approaches do not require any specific equipment or skill, but just leverage developments made for functional verification Qualifications of the instructor
He was General co-Chair for DFT'02, vice General Chair for IOLTW'02, Program co-Chair for DFT'01, IOLTS'04 and IOLTS'06, vice Program Chair for IOLTS'03, IOLTS'05 and IOLTS'07, Industrial Co-Chair for ETS'12, and Topic Chair for ETS'08, ETS'09, ETS'10, ETS'14, ETS'15 and ETS'16. He is a Senior member of IEEE. Contact:
Régis
LEVEUGLE
Challenges of FPGA-Based Prototyping & Debugging AbstractSoftware has come to dominate system-on-chip (SoC) development. It is increasingly common for the software effort to be on the critical path of the project schedule. Only FPGA-based prototyping provides both the speed and accuracy necessary to develop and validate complex software integration prior to silicon. The exciting benefits of an FPGA-based prototype are:
So if your designs are getting larger and more complex than ever, if you need to build and validate systems with millions gates count that exceed the performance and capacity limits of the traditional SW-Simulators and if your system contains pre-built design IPs and SW components that need to have a fully functioning hardware platform as early as possible. We invite you to join us for FPGA-Based Prototyping Tutorial where you will get introduced to the major challenges in FPGA-Based prototyping and debugging. Our tutorial will cover: Introduction: An Overview about the latest FPGA Verification Technology Adoption Trends will be addressed as well as the basics of FPGA flow. FPGA-Based Prototyping: Prototyping next-generation SoCs, which contain more functionality than the capacity offered by a single FPGA, means spreading that functionality across multiple FPGAs, leading to challenging partitioning and timing closure issues. Traditional prototyping solutions manage device under test (DUT) partitioning either at the RTL level or at the gate level, but they fail to offer a predictable and efficient flow that would allow the FPGA-based SoC prototype to be brought up quickly. VPS (Veloce Prototyping System) tackles FPGA-based prototyping challenges and offers SoC designers an innovative methodology unifying the benefits of gate-level partitioning and RTL partitioning, providing a short, automated, and predictable path to prototype Multiple FPGA Prototyping Challenges: Multi-FPGA partitioning is a complex optimization problem that must handle multiple constraints and concurrent objectives. The partitioning challenges that have to be overcome to make FPGA-based prototyping effective are: Heterogeneous FPGA logic resources management, Unbalanced interconnect management and pin multiplexing, Timing closure issues and timing constraints generation, Incremental flow for fast turnaround, Full system verification and simulation as well as Bug hunting methodologies FPGA Debugging: Recall that, to debug an FPGA prototype, probes are added directly to the RTL design to make specific signals available for observation, synthesized and downloaded to the FPGA prototype platform. Fortunately, major FPGA vendors today have internal logic analyzers to address the visibility issue. However, many of these internal logic analyzers have several limitations, including support for only single FPGA debug, limited memory size using FPGA internal memory, and long place-and-route times to change probes while large SoCs efficient debugging often requires concurrent access to hundred thousand or more of design signals. Accordingly we will demonstrate how advanced FPGA debugging techniques allow thousands of signals to be traced with huge trace depth by the use of highly efficient multi-stage concentrator as the basis for its observation network, employing data compression on the trace data to overcome the limited RAM resources in any FPGA, or streaming FPGA run trace to external memory or directly to the host via a fast connection buses. Design Challenges for FPGA some insights about the long initial time required for bringing up the prototype and how setting up a design for FPGA prototype may be a time-consuming activity that includes error-prone sub-tasks, hence a careful planning is required in order to accomplish prototyping goals with minimal effort. Qualifications of the instructors
Her PHD graduation thesis is about “Exploring
Machine Learning techniques in Functional
Verification Field”, she had been certified as Green
Belt Six Sigma for Information Technology and
Software Engineering from the European Software
Institute (ESI) and Certified Quality Manger and
Organizational Excellence from American Society of
Quality. She published number of articles in the
field of assertion based verification, machine
learning and Software testing.
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Important Dates
Regular Paper
Submission
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