The 30^th International Conference on Microelectronics (ICM2018)

About ICM2018

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The International Conference on Microelectronics (ICM) has been held in numerous countries across the Southern Europe and Western and Southern Asia for the past 29 years. The 30^th edition of the conference will be hosted by Computer and Embedded Systems Laboratory (CES lab) in Tunisia. In ICM 2018, several topics will be discussed such as Circuits and Systems, CAD Tools and Design and Micro/Nano electronics and special topics. It will include oral, poster sessions and tutorials given by experts in state-of-the-art topics. The regular technical program will run for three days. Moreover tutorial sessions will be held on the first day of the conference. Perspective authors are invited to upload full papers using the ICM2018 Electronic Submission Portal below.

Call for papers

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You are invited to upload full papers using the ICM2018 Electronic Submission Portal below. Regular papers should be prepared with the official IEEE paper template of no more than 4 pages including results, figures and references. Your submission should contain sufficient details to allow for critical review. All submissions will be evaluated by at least two reviewers.
Papers are solicited in, but not limited to, the following topics:

Keynotes/ Tutorials

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KEYNOTES:
ICM 2018 keynotes include:

• Neural Signal Recording Amplifiers

• A Self-powered IoT SoC Platform for Wearable Health Care

• Flexible Radios and Flexible Networks

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Keynote Speaker1

Neural Signal Recording Amplifiers

Abstract
Wearable and implantable medical devices have shown great benefits in monitoring health conditions and combating various diseases that cannot be cured by conventional medical means. The physiological and neural signal acquisition is at the very front end of such devices, and its performance is critical to the overall system. This talk will start with a quick introduction of the neural signal recording, followed by several neural recording amplifier designs, in which different circuit techniques are employed to improve the performance. The talk will conclude with the recent trend in neural signal recording amplifier design.

Qualifications of the speaker

Dr. Yong Ping Xu received his PhD in Electrical Engineering from the University of New South Wales, Australia, in 1994. He was a Lecturer at University of South Australia, Adelaide, from 1996 to 1998. He joined the Department of Electrical & Computer Engineering, National University of Singapore (NUS) in 1998 and is now an Associate Professor. His research interests include integrated circuit design for MEMS, sensors, and biomedical applications. Dr Xu isa member of Technical Program Committee of 2017 Symposium on VLSI Circuits (VLSI). He served ITPC of IEEE International Solid-State Circuits Conference (ISSCC) from 2014 to 2018 and the TPC of IEEE Asian Solid-State Circuits Conference (A-SSCC) from 2009 to 2013.

He was the Organizing Committee Chair for A-SSCC 2013 in Singapore and has been a member of A-SSCC Steering Committee since 2014.Dr Xu is a Distinguished Lecturer of IEEE Solid-State Circuits Society (2017 and 2018).

Keynote Speaker2

A Self-powered IoT SoC Platform for Wearable Health Care

Abstract
This talk will focus on an IoT Systems-on-Chip (SoCs) as part of research work which targets applications in self-powered chip sets for use in public health, ambient intelligence, safety and security and IoT.
One such application, which we will discuss in details, is a ground breaking self-powered IoT SoC platform for wearable health care. More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system. The system achieved an accuracy of 99%.The ECG signal is sensed using a flexible, dry, Graphene-based technology and the system is powered up by harvesting human thermal energy. The system architecture is implemented in Global foundries’ 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating frequency of10 KHz and from a supply voltage of 1.2V. To our knowledge, this is the first SoC implementation of an ECG-based processor that is capable of predicting ventricular arrhythmia hours before the onset and with an accuracy of 99%.

Qualifications of the speaker

Pr. Mohamed Ismail is a professor and Chair of ECE at Wayne State University, Detroit, Fellow IEEE, Adjunct professor with KUSTAR, Abu Dhabi, UAE. Prof. Mohammed is a prolific author and entrepreneur in the field of chip design / test and nanotechnology, spent over 25 years in academia and industry in the US and Europe He obtained his BS and MS from Cairo University, Egypt and His PhD from the University of Manitoba, Canada , all in electrical engineering. He held a Research Chair on nano-electronics circuits at the Swedish Royal Institute of Technology (KTH) where he founded the RaMSiS Research Group there. He had visiting appointments in Finland (Aalto university), Norway (NTH and University of Oslo), the Netherlands (Twente University) and Japan (Tokyo Institute of Technology).

He is the Founder of the Ohio State University's (OSU) Analog VLSI Lab, one of the foremost research entities in the fields of analog, mixed signal and RF integrated circuits and served as its Director.
He Joined KUSTAR, the UAE in 2011, where he held the ATIC (now Mubadala Technology) Professor Chair and is Founding Chair of the ECE Department. He is the Founding Director of the Khalifa Semiconductor Research Center (KSRC) . His current research focuses on CMOS RF and mm-wave ICs , energy harvesting and power management, wearable Biochips and Systems on Chip ( SoCs) for the Internet of Things ( IoTs) and smart self-driving vehicles. He joined Wayne State University in Detroit, MI,USA as professor and Chair of ECE while maintaining his position at KUSTAR as an Adjunct.
He leads a research team that developed the first CMOS combo 802.11a/b/g Wi-Fi Radio chip which was commercialized. More recently He developed with his colleagues the world first self-powered wearable device that predicts the onset of a heart attack long before it happens and is currently in the process of commercializing it in partnership with the Cleveland Clinic, a world leading hospital in cardiology. He advised the work of over 50 Ph.D. students and of over 100 M.S. students. He authored or co-authored over 20 books and over 170 journal publications, 300 conference papers and has 15 US patents granted and several pending.

Keynote Speaker3

Flexible Radios and Flexible Networks

Abstract
Over the past decades the world has become increasingly connected, with communications driving bothmarkets and social movements. Low power electronics, efficient communications, and better battery technology have all contributed to this revolution, but the cost and power required for these systems must be pushed further to make cheap, ubiquitous, seamless communication accessible to a wider community. In this talk I will discuss two engineering approaches to this problem. I will look at various approaches to drive the power down in radio networks that span across circuits and systems. I will also look at creative biologically inspired approaches to enabling very low power networks and IoT. Finally, I will discuss how by adding flexibility and building reconfigurable hardware, we can likewise build lower power and less costly consumer systems that can adapt across protocols and networks and work under changing device technologies.

Qualifications of the speaker

Dr. Alyssa Apsel received the B.S. from Swarthmore College in 1995 and the Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002. She joined Cornell University in 2002, where she is currently Director of Electrical and Computer Engineering. She was a Visiting Professor at Imperial College, London from 2016-2018. The focus of her research is on power-aware mixed signal circuits and design for highly scaled CMOS and modern electronic systems. Her current research is on the leading edge of ultra-low power and flexible RF interfaces for IoT.

She has authored or coauthored over 100 refereed publications including one book in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in ten patents. She received best paper awards at ASYNC 2006 and IEEE SiRF 2012, had a MICRO “Top Picks” paper in 2006, received a college teaching award in 2007, received the National Science Foundation CAREER Award in 2004, and was selected by Technology Review Magazine as one of the Top Young Innovators in 2004. She is a Distinguished Lecturer of IEEE CAS for 2018-2019, and has also served on the Board of Governors of IEEE CAS (2014-2016) and as an Associate Editor of various journals including IEEE Transactions on Circuits and Systems I and II, and Transactions on VLSI. She has also served as the chair of the Analog and Signal Processing Technical committee of ISCAS 2011, is on the Senior Editorial Board of JETCAS, as Deputy Editor in Chief of Circuits and Systems Magazine, and as the co-founder and Chair of ISCAS Late Breaking News. In 2016, Dr. Apsel co-founded AlphaWave IP Corporation, a multi-national Silicon IP provider focused on multi-standard analog Silicon IP solutions for the world of IOT. As Chief Technology Officer of AlphaWave, Dr. Apsel led the company’s global research capability with offices in Silicon Valley, Toronto, and London.

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TUTORIAL SESSIONS:

ICM 2018 Tutorials include:

• Cyber-physical system design challenges

• Machine Learning for EDA

• Automotive Digital Twin: ADAS System verification

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Tutorial1: Cyber-physical system design challenges

Abstract
Due to major breakthroughs in software and engineering technologies, embedded systems are increasingly being utilized in areas ranging from aerospace and next-generation transportation systems, to smart grid and smart cities, to health care systems, and broadly speaking to what is known as Cyber-Physical Systems (CPS). A CPS is primarily composed of several electronic, communication and controller modules and some actuators and sensors. The mix of heterogeneous underlying technologies poses a number of technical challenges to the design and more severely to the verification of such complex infrastructure. In fact a CPS shall adhere to strict safety, reliability, performance and security requirements, where on needs to capture both physical and random aspects of the various CPS modules and then analyze their inter-relationship. Oftentimes however, system bugs remain uncaught during the analysis and in turn cause unwanted scenarios that may have serious consequences in safety critical applications. In this keynote talk, we introduce some of the challenges surrounding the design and verification of contemporary CPS with the advent of smart technologies. In particular, we will introduce recent developments in the use of formal methods for the modeling, analysis and verification of CPS and display a few real world CPS case studies using physical components based on photonics integrated circuits.

Qualifications of the instructor

Prof. Sofiène Tahar is Professor and Senior Research Chair in the Department of Electrical and Computer Engineering at Concordia University, Montreal, Quebec, Canada. He received his PhD degree in Computer Science with “Distinction” in 1994 from the University of Karlsruhe and his Diploma degree in Computer Engineering in 1990 from the University of Darmstadt, Germany. Prof. Tahar is founder and director of the Hardware Verification Group (http://hvg.ece.concordia.ca) at Concordia University. He has made contributions and published over 400 papers in the areas of formal hardware verification, microprocessor and system-on-chip verification, analog and mixed signal circuits verification, VLSI design automation, and formal probabilistic,statistical and reliability analysis of systems.

Prof. Tahar has received several awards and distinctions, including in 2007 Concordia University’s Senior Research Award earning him the title of University Fellow. In 2010, he was the recipient of a national Discovery Accelerator Award,given to the top 100 researchers in Canada in engineering and sciences. He is member of the Order of Engineers of Quebec, Senior member of IEEE and Senior member of ACM.

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Tutorial2: Machine Learning for EDA

Abstract
Machine learning and deep learning become a new evolving addition to the field of design and design automation flows. This tutorial covers machine learning as well as deep learning algorithms and application methodologies that are necessary to build EDA applications and flows. The tutorial starts with classical machine learning methods. This is followed by introduction to deep learning algorithms and motivation behind why deep learning starts taking off. Finally, the tutorial is concluded by demonstrating how the different ML/DL algorithms can be applied to solve some practical EDA problems, namely in the fields of functional verification and physical verification.
Description
The tutorial includes three major parts:
    1.   Part1: Introduction to Classical Machine Learning
    2.  Part2: Introduction to Deep Learning
    3.  Part3: Application to Common EDA Problems

Qualifications of the instructor

Dr. Eman El Mandouh is Quality Director for IC Verification and Validation Solutions Division, Mentor Graphics Siemens Business. She has more than 18 years of experience in the field of digital design and functional verification technology, namely simulation based verification, advanced formal verification solutions, coverage driven verification, intelligent test generation, FPGA Prototype & Debugging. She received her PHD in 2018, from Cairo University, Computer Engineering where she obtained her B.Sc. and M.Sc. Her PHD graduation thesis is about “Exploring Machine Learning techniques in Functional Verification Field”, she has published number of articles in the field of functional verification, machine learning, data mining, big-data techniques with function verification and Software testing.

Working as quality manager for EDA, Eman has been certified from world quality institutes such as Green Belt Six Sigma for Information Technology and Software Engineering from the European Software Institute (ESI) and Quality Manger and Organizational Excellence from American Society of Quality.

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Tutorial3: Automotive Digital Twin: ADAS System verification

Abstract
Automotive Original Equipment Manufacturers (OEMs) are taking more control of Electronic Control Unit (ECU) hardware/software architecture definition and exploration mainly due to the rise of new technologies in ADAS and autonomous vehicles. The increasing number of cars with ECUs containing tens of processors, and the need to accelerate the simulation of thousands of driving scenarios and design parameters to ensure safety and reliability in autonomous driving has expanded the use of hardware emulation in the loop based on its capacity and functional verification merits. In this presentation, an integrated heterogeneous system of systems framework to simulate and verify multiple ECUs is presented. The framework allows co-development of the automotive system application software, operating system and controller hardware together with the mechanical system actuators, sensors, and the physical world environment/traffic scenarios all in one. A comprehensive manual/automatic braking system use case consisting of four ECUs at different levels of abstraction is used to demonstrate the tools and interface technologies developed in-house and integrated with third-party tools. The first dashboard ECU acts as a CAN frame monitor and exerciser. The second engine control ECU is modeled as a virtual platform running an AUTOSAR software stack and engine control application. The third transimission controller ECU (digital subsystem) is modeled in Register Transfer Language (RTL) and a Bare-Metal application on a RISC-V running in a hardware emulator. The mechanical part of the braking system is modeled and exported as a Functional Mockup Unit (FMU) and connected to the hardware emulator using an FMI Transport Application (FMITAP) that is based on SystemC TLM 2.0 & FMI 2.0. The fourth ADAS Control ECU is modeled as a virtual platform running an automated emergency braking system application. This platform is wrapped as an FMU and imported together with Sensor and ADAS Scenarios. The effect of a crossing traffic scenario can be easily simulated, tracked and analyzed in all ADAS control loop elements.

Qualifications of the instructor

Dr. Ashraf Salem is Engineering Director in Mentor Graphics Egypt. He manages a group of 200 engineers working in the development of Emulation, Simulation Embedded Systems and Automotive products. Dr. Salem obtained his Ph.D. from Grenoble University, France in 1992. He got his B.Sc. and M.Sc. in Computer Engineering from Ain Shams University in 1983, 1987 respectively. He was the CEO of the Technology Innovation and Entrepreneurship Center (TIEC) and professor of Computer Engineering, Faculty of Engineering, Ain Shams University. Dr. Salem participated in the establishment of ANACAD branch in Egypt in 1995 that then has been acquired by Mentor Graphics and became one of the largest multinational development centers.

Dr. Salem participated in the establishment of Software Engineering Competence Center and Information Technology Institute in Egypt. He published more than 120 scientific articles in the fields of Computer Aided design of Digital circuits. He chaired the technical committees in a number of international conference, and he supervised more than 20 PhD and M. Sc. thesis in digital design and Embedded systems. Also, he participated in a number of international research projects and developed one of the pioneer research products for formal verification in the eighties.

Organizing Committee

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Important Dates

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Submission

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We invite Research Papers submission to the conference which should not exceed 4 pages using the IEEE Standard template without page numbers:
http://www.ieee.org/conferences_events/conferences/publishing/templates.html
The full papers should be submitted in PDF format through the online submission system EasyChair

Papers accepted for Oral Presentation will be submitted for inclusion in the IEEE Xplore Digital Library.
IEEE reserves the right to exclude a paper from distribution after the conference, including IEEE Xplore® Digital Library, if the paper is not presented by the author at the conference.

Instructions for Camera ready preparation
To prepare your camera ready, please follow the instructions mentioned in this file

Copyright submission

Registration

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Registration rules
All the ICM2018 conference authors have to register and pay the applicable fee for a paper to be published in the conference proceeding.
Please note that every paper must be registered at Regular rate to get it published.
One registration covers two papers at maximum.
The paper registration will be considered once all fees have been paid.
The accepted but not presented manuscripts will not be included in the conference proceedings.
The deadlines for registration in ICM 2018 are as follows:
- Early Registration deadline is due by November 10, 2018
- Late Registration deadline is due by December 04, 2018
Please note that additional fees will be added in the case of late registration.

Instructions for registration and fees:

Fill in this online form
For more information, please feel free to contact contact@ieee-icm2018.org.

Instructions for presentation slides and posters preparation
To prepare your presentation slides, please follow the instructions mentioned in the presentation rules
To prepare your poster, please follow the instructions mentioned in the poster recommendations and use the poster template